1. Field of the Invention
The present invention relates generally to integrated circuits, and more particularly to methods and apparatuses for amplifying signals sensed from selected memory locations.
2. Description of the Related Art
As is well known in the art, random access memory (RAM) devices are generally array structures composed of 2.sup.n by 2.sup.m individual RAM cells which are coupled to wordlines (rows) and complementary bit lines (columns). A typical RAM memory cell may be composed of between 4 and 6 transistors coupled together to form a data storage device. An individual RAM memory cell may be selected when an X-decoder is used to select rows and a Y-decoder is used to select columns. Typically, data is written into an individual RAM cell when the proper address is selected and a WRITE ENABLE circuitry allows digital data in the form of a differential voltage signal to be input into a selected memory cell location. As is well known in the art, once a specific memory cell is addressed within a RAM device and a READ ENABLE circuitry is active, a very small voltage amplitude representing the addressed digital data is sensed. However, to produce a readable voltage amplitude representing useful digital data, a sense amplifier is typically implemented to amplify the sensed signal.
FIG. 1 shows a conventional RAM block diagram used for outputting digital data stored within a RAM core 100. By way of example, when RAM core 100 includes 1,000 rows by 1,000 columns, RAM core 100 may be classified as a one megabit (1 MB) RAM storage device. In typical architectures, computers access RAM core 100 through an address input bus 110 that may be coupled to a conventional X-DECODER 102 and a conventional Y-DECODER 104. In general, X-DECODER 102 is used for addressing a selected row (wordlines) within RAM core 100, and Y DECODER 104 is used for addressing a selected column (bitlines) within RAM core 100. By way of example, X and Y decoders are generally implemented for reducing memory array aspect ratios by folding (i.e., dividing) long addressable memory columns into several shorter memory columns. Once folded into several columns, the X and Y decoders are capable of reading or writing the addressed data by appropriately performing a suitable multiplexing function.
Once a row and column is selected from RAM core 100, either a write or a read operation may be performed on the selected RAM memory cell. In order to perform a write operation, a write control circuit 107 is enabled which allows digital data to be input into a selected RAM memory cell via an input data bus 101. Generally, this digital data is in the form of a voltage waveform that represents either a logical "1" or a logical "0". Input buffer 109 amplifies a input signal 103 that is supplied by RAM input bus 111. In this manner, the selected transistors in RAM core 100 may be driven to an appropriate state.
In a like manner, once the row and column is selected in RAM core 100, a read operation may be performed which produces a voltage representing the addressed digital data on a data bus 112. At this point, the addressed digital data may be as low as about 50 milli-volts (mV). As described above, to appropriately read the addressed digital data, suitable amplification is typically performed in a sense amplifier 106. Once the sensed data signal is amplified to full rail voltage level (i.e., about 3.3 volts or about 5 volts) in sense amplifier 106, the voltage amplified data is passed out as amplified data output 114 to an output buffer 108. At output buffer 108, the voltage amplified data 115 is current amplified to provide an appropriate level of current drive once the read data is passed to a RAM output bus 116.
There are a variety of well known conventional sense amplifiers 106, however, most conventional sense amplifiers 106 are not well optimized for performing fast read operations once data is sensed on data bus 112. In addition, conventional sense amplifiers are generally somewhat sluggish in recovering after the successful read operation has been performed. As is well known in the art, in order to perform a successful read/write operation, the nodes of a sensed data bus (i.e., SD and /SD) must be pulled apart somewhere between Vss (i.e., 0 volts) and V.sub.CC (i.e., 3.3 or 5 volts). That is, to accurately define a "1-bit" or a "0-bit", the sensed data (SD) node must be, for example, pulled towards V.sub.CC, and the sensed data (/SD) node must be, for example, pulled towards V.sub.SS. Unfortunately, most conventional sense amplifiers suffer in that SD and /SD are pulled apart too slow for speed sensitive applications.
Once SD and /SD are adequately pulled apart to complete a successful read operations, the sensed data nodes SD and /SD must be switched back to their original state (i.e., a ready to read state). That is, the nodes of the sensed data bus must be equalized (i.e., pulled back together) to their original voltage levels. Consequently, the next operation may not be performed until the nodes of the sensed data bus are equalized. It is therefore important to realize that most conventional sense amplifiers lack the ability to quickly amplify sensed data by rapidly pulling SD and /SD apart as well as the ability to rapidly restore the sensed data bus to its "ready" state.
In view of the foregoing, there is a needed for methods and apparatuses for rapidly amplifying sensed data signals read from memory locations. In addition, there is a need for methods and apparatuses for rapidly recovering a sense amplifier to a "ready to read" state after a previous operation is complete.